Fast FPGA-Based Multipliers by Constant for Digital Signal Processing Systems
نویسندگان
چکیده
Traditionally, the usual multipliers are used to multiply signals by a constant, but multiplication constant can be considered as special operation requiring development of specialized multipliers. Different methods being developed accelerate multiplications. A large list implement on group bits. The most known one is Booth’s algorithm, which implements two-digit multiplication. We propose modification algorithm for three digits at same time. This solution reduces number partial products and accelerates multiplier. paper presents results comparative analysis characteristics proposed algorithm. Additionally, comparison with built-in FPGA illustrated.
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ژورنال
عنوان ژورنال: Electronics
سال: 2023
ISSN: ['2079-9292']
DOI: https://doi.org/10.3390/electronics12030605